The combined application of stress, temperature, and bias has the potential to enhance FRAM (ferroelectric random access memory) performance at the 130-nm technology node and possibly extend the technology to the 90-nm node and beyond. While temperature and bias have been traditionally used to pole ferroelectric thin-films, applied stress has also been shown to enhance ferroelectric properties. This can lead to an improved FRAM signal margin, which is a key metric for FRAM reliability and performance. We propose to comprehensively study the effects of stress, temperature, and bias on the ferroelectric properties of fully integrated thin-film PZT ferroelectric capacitors. These effects will be investigated experimentally. We will then develop SPICE simulation models and simulate the stress in ferroelectric films based on TI’s 130-nm process. Our goal is to gain a deep understanding of the underlying physics of stress effects at bias and temperature on ferroelectric capacitors, and use this knowledge to develop accurate models that can simulate these effects and be used in FRAM design. We will then recommend strain-engineering methods for enhancing FRAM performance at the 130-nm node and beyond.
Advancing FRAM technology beyond the 130-nm node can increase storage density and reduce cost, leading to new potential markets and applications. However, further scaling of ferroelectric PZT films can diminish FRAM performance. It has been suggested that scaling beyond the 130-nm technology node will require different FRAM structure and materials, which can lead to increased costs and development time. We propose that stress engineering may be a solution to enhance current FRAM technology and extend it to the 90-nm node and beyond.