For the past four decades the chip industry has been able to keep pace with Moore's Law by the physical scaling of transistors. This has lead to an increase in speed and performance with each new generation. However, with scaling soon to reach its limits alternate technologies will be needed to sustain and extend Moore's Law. One of the more viable technologies is strained silicon and it is already being used in commercial integrated circuits. This project aims to maximize the amount of strain possible in semiconductor devices and to also incorporate strain into the next technological vector. We plan to accomplish this by:

• Investigating and determining the optimal stress level in strained silicon devices for mobility enhancement
• Developing semiconductor devices on flexible substrate to maximize strain due to bending
• Investigating the effects of stress on III-V devices

• Be able to design chips for maximum output enhancement via straining
• Complex circuits for flexible electronics applications
• Heterogenous integration of strained III-V materials into CMOS technology

• Be able to apply stress upwards of 1.5 GPa to semiconductor devices
• Reliable data on the effects of strain on III-V devices